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microprocessor supervisory circuit R5107G series no. ea-170-070908 1 outline the R5107G series are cmos-based con supervisory circuit, or high accuracy and ultra low supply current voltage detector with built-in delay and watchdog timer. when the vdd voltage is down across the threshold, or the watchdog timer does not detect the system clock from the con, the reset output is generated. the voltage detector circuit is used for the system reset, etc. the detector threshold is fixed internally, and the tolerance is 1.0%. the released delay time (power-on reset delay) circuit is built-in, and output delay time is adjustable with an external capacitor. when the vdd supply voltage becomes higher than the released voltage, the reset state will be maintained during the delay time. the time out period of the watchdog timer can be also set with an external capacitor. the output type of the reset is selectable, nch open-drain, or cmos. the function to stop supervising clock by the watchdog timer (inh function) and manual reset function are built in this ic. the package is small ssop-8g. features ? built-in a watchdog timer's time out period accuracy 30% ? timeout period for watchdog and generating a reset signal can be set by an external capacitor ? detector threshold voltage 0.1v stepwise setting in the range from 1.5v to 5.5v ? supply current typ. 11a ? operating voltage 0.9v to 6.0v ? high accuracy output voltage of detector threshold 1 .0% ? power-on reset delay time accuracy 20% ? power-on reset delay time of the voltage detector can be set with an external capacitor. ? small package ssop-8g (0.65mm pitch) application ? supervisory circuit for equipment with using microprocessors.
R5107G ( preliminar y) 2 block diagrams R5107Gxx1a R5107Gxx1c tw gnd vdd sck resetb clock detector watchdog timer - + inh - + mr cd tw gnd vdd sck resetb clock detector watchdog timer - + inh - + mr cd
R5107G ( preliminar y) 3 selection guide the selection can be made with designating the part number as shown below: R5107Gxx 1x-tr part number ab c d code descriptions a designation of package type; g: ssop8g (2.9mmx4.0mm) b designation of detector threshold voltage (-v det ) 0.1v stepwise setting is possible in the range from 1.5v to 5.5v c designation of the output type of resetb a: nch open-drain c: cmos output d designation of taping type pin configuration ssop8g (0.65mm pitch) pin description pin no symbol pin description 1 resetb output pin for reset signal of watchdog timer and voltage detector. (output ?l? at detecting detector threshold and watchdog timer reset.) 2 mr manual reset pin (active at "l") 3 c d external capacitor pin for setting delay time of voltage detector 4 gnd ground pin 5 sck clock input pin from microprocessor 6 inh inhibit pin ("l": inhibit the watchdog timer) 7 tw external capacitor pin for setting reset and watchdog timeout periods 8 v dd power supply pin 1 2 3 8 7 6 sck inh vdd tw resetb gnd cd mr R5107Gxxxa R5107Gxxxc 4 5
R5107G ( preliminar y) 4 absolute maximum ratings topt=25 c, v ss =0v symbol item rating unit v in supply voltage -0.3 7.0 v v cd voltage of c d pin -0.3 v in +0.3 v v tw voltage of tw pin -0.3 v in +0.3 v v resetb output voltage voltage of resetb pin -0.3 7.0 v v sck voltage of sck pin -0.3 7.0 v v inh voltage of inh pin -0.3 7.0 v v mr input voltage voltage of mr pin -0.3 7.0 v i resetb output current current of resetb pin 20 ma p d power dissipation 300 mw topt operating temperature range -40 +105 c tstg storage temperature range -55 +125 c electrical characteristics R5107Gxxxa/c unless otherwise specified, v in =6.0v, c tw =0.1uf, c d =0.1uf, rpull-up=100k ? (R5107Gxxxa) the number of bold font applied to the temperature range from -40 c to 105 c (topt=25 c) symbol item conditions min. typ. max. unit v in operating voltage 0.9 6.0 v iss supply current v in =(-v det )+0.5v clock pulse input 11 15 a voltage detector -v det detector threshold sense pin threshold x0.990 x0.972 x1.010 x1.015 v ? -v det / ? topt detector threshold temperature coefficient -40 c topt 105 c 100 ppm/ c v hys detector threshold hysteresis (-v det ) x0.03 (-v det ) x0.05 (-v det )x 0.07 v tp lh output delay time c d =0.1 f 340 370 467 ms i doutn output current (resetb output pin) nch, v dd =1.2v, v ds =0.1v 0.38 0.80 ma i doutp output current (resetb output pin) nch, v dd =6.0v, v ds =0.5v(r5108gxxxc) 0.65 0.90 ma v mrh mr input "h" 1.0 6.0 v v mrl mr input "l" 0.00 0.35 v mrw mr input pulse width (*note1) 2 us rmr mr pull-up resistance 60 110 164 k ? watchdog timer t wd watchdog timeout period c tw =0.1uf 230 310 450 ms t wr reset hold time of wdt c tw =0.1uf 29 34 48 ms
R5107G ( preliminar y) 5 symbol item conditions min. typ. max. unit v sckh sck input "h" v in x0.8 6.0 v v sckl sck input "l" 0.0 v in x0. 2 v v inhh inh input "h" 1.0 6.0 v v inhl inh input "l" 0.00 0.35 v r inh inh pull-up resistance 60 110 164 k ? t sckw sck input pulse width v sckl =v in x0.2, v sckh =v in x0.8 500 ns *bold type value is guaranteed by design. *note1: mr input pulse width specification guarantee the minimum input pulse width of mr pin for output "l" from resetb pin. if the "l" pulse width of mr is short, tplh may be short. refer to the timing diagram for details. typical applications power supply sw r c tw c cd sw R5107Gxxxa series gnd v dd c d resetb sck tw mr inh p v dd i/o reset power supply sw c tw c cd sw R5107Gxxxc series gnd v dd c d resetb sck tw mr inh p v dd i/o reset
R5107G ( preliminar y) 6 test circuit supply current test circuit clock input R5107Gxxxa/c series gnd v dd c d resetb sck tw mr inh c cd c tw r(R5107Gx xxa) a
R5107G ( preliminar y) 7 timing diagram (R5107Gxxxa/R5107Gxxxc) (nch open-drain, resetb pin is pulled up to v dd .) v dd tw sck vrefh vrefl n resetb tplh +v det (1) (2) (4) (3) (5) (6) twr -v det tphl mr c d vtcd twd tplh twd twr twdi tmr
R5107G ( preliminar y) 8 operation when the vdd pin voltage becomes more than the released voltage (+v det ), after the released delay time (or the power on reset time tplh), the output of resetb becomes ?h? level. when the sck pulse is input, the watchdog timer is cleared, and tw pin mode changes from discharge mode to charge mode. when the tw pin voltage becomes higher than vrefh, the mode will change into discharge, and next watchdog time count starts. unless the sck pulse is input, wdt will not be cleared, and during the charging period of tw pin, resetb="l". when the vdd pin becomes lower than the detector threshold voltage, resetb outputs "l". if "l" signal is input to the mr pin, the resetb outputs "l", regardless the sck clock state and v in voltage. when the signal to the mr pin is set from "l" to "h", the watchdog starts supervising the system clock. mr c d resetb complete discharge power on reset operation with mr pin input ( tplh1 < tplh ) +v tcd -v tcd tplh tplh1 0v 0v 0v incomplete discharge tplh v dd c d resetb complete discharge det +v +v tcd tcd tplh1 power on reset operation against the input glitch (tplh1 < tplh ) 0v 0v 0v incomplete discharge -v det -v
R5107G ( preliminar y) 9 ? watchdog timeout period/reset hold time the watchdog timeout period and reset hold time can be set with an external capacitor to tw pin. the next equations describe the relation between the watchdog timeout period and the external capacitor value, or the reset holding time and the external capacitor value. t wd(s) = 3.1*10 6 c (f) twr(s)=twd/9 the watchdog timer (wdt) timeout period is determined with the discharge time of the external capacitor. during the watchdog timeout period, if the clock pulse from the system is detected, wdt is cleared and the capacitor is charged. when the charge of the capacitor completes, another watchdog timeout period starts again. during the watchdog timeout period, if the clock pulse from the system is not detected, during the next reset hold time resetb pin outputs "l". after starting the watchdog timeout period, (just after from the discharge of the external capacitor) even if the clock pulse is input during the time period "twdi", the clock pulse is ignored. twdi[s]=twd/10 released delay time (power-on reset delay time) the released delay time can be set with an external capacitor connected to the cd pin. the next equation describes the relation between the capacitance value and the released delay time (tplh). tplh(s)=3.7 10 6 c(f) note that the temperature dependence graph in the typical characteristics does not contain the temperature characteristics of the external capacitor. when the vdd voltage becomes equal or lower than -v det , discharge of the capacitor connected to cd pin starts. in case that the discharge is not enough, if the v dd voltage returns equal or more than (+v det ), the delay time tplh will be shorter than expected. minimum operating voltage (vinl) we specified the minimum operating voltage as the minimum input voltage in which the condition of resetb pin being 0.1v or lower than 0.1v. (herein, pull-up resistance is set as 100k ? in the case of the nch open-drain output type. inhibit (inh) function if inh pin is set at "l", the watchdog timer stops monitoring the clock, and the resetb output will be dominant by the voltage detector's operation. therefore, if the equal or more than the detector threshold level is input, resetb outputs "h" regardless the clock pulse. inh pin is pulled up with a resistor (typ. 110k ? ) internally. manual reset function by setting mr pin as "l", the output of resetb can be forced to set "l". after pull-down the mr pin to "l", the delay time (dmr) to the output "l" from resetb is 1us as maximum. mr pin is pulled-up via the built-in resister. (typ. 110k ? ). if mr pin voltage> vin voltage, a current flows into mr pin. however, the current value is limit by the pull-up resister, therefore there is not bad impact on the operation. when the "l" signal is input to mr pin, the discharge of cd pin capacitor (c cd ) starts. if the term of "l" for mr pin is short, c cd will not be discharged enough. as a result, the delay time after setting "h" for mr pin will be shorter than expected. because of this, confirm the operation under the same conditions as users' applications. for example, in case of c cd is set at 0.1uf, and the condition to maintain the delay time value after mr pin's returning to "h", is described as the minimum "l" term of mr pin, or 150us. resetb output resetb pin's output type is selectable either the nch open-drain output or cmos output. if the nch open-drain type output is selected, the resetb pin is pulled up with an external resistor to an appropriate voltage source.
R5107G ( preliminar y) 10 clock pulse input built-in watchdog timer is cleared with the sck clock pulse within the watchdog timeout period. application notes if a resistor is connected to the vdd pin, the operation might be unstable with the supply current of ic itself. typical characteristics 1) supply current vs. input voltage 2) detector threshold vs. temperature connection examples affected by the conduction current r5108 vdd vin r1 resetb r5108 vdd vin r1 resetb r2 v in r5108 cmos output v dd r1 r2 resetb r 5 1 0x n 1 5 1 a/ c , r 5 1 0xg 1 5 1 a/ c 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 20 0 1 23456 s upp l y v o lt ag e [ v ] c u rrent i ss [ua] 25 1 05 - 50 r 5 1 0x n 30 1 a/ c , r 5 1 0xg30 1 a/a 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 20 0 1 23456 s upp l y v o lt ag e [ v ] c u rrent i ss [ua] 25 - 50 1 05
R5107G ( preliminar y) 11 3) detector threshold hysteresis vs. temperature r 5 1 0x n 1 5 1 a/ c , r 5 1 0xg 1 5 1 a/ c 1 . 4 7 0 1 . 480 1 . 4 9 0 1 . 500 1 . 5 1 0 1 . 520 1 . 530 - 50 - 25 0 25 50 7 5 1 00 1 25 tem p er a t u re [ ] detect v o lt ag e [ v ] r 5 1 0x n 2 7 1 a/ c , r 5 1 0xg2 7 1 a/ c 2 . 660 2 . 6 7 0 2 . 680 2 . 6 9 0 2 .7 00 2 .7 1 0 2 .7 20 2 .7 30 2 .7 40 - 50 - 25 0 25 50 7 5 1 00 1 25 tem p er a t u re [ ] detect v o lt ag e [ v ] r 5 1 0x n 42 1 a/ c r 5 1 0xg42 1 a/ c 4 . 1 20 4 . 1 40 4 . 1 60 4 . 1 80 4 . 200 4 . 220 4 . 240 4 . 260 4 . 280 - 50 - 25 0 25 50 7 5 1 00 1 25 tem p er a t u re [ ] detect v o lt ag e [ v ] r 5 1 0x n 1 5 1 a/ c r 5 1 0xg 1 5 1 a/ c 3 . 0 4 . 0 5 . 0 6 . 0 7. 0 - 50 - 25 0 25 50 7 5 1 00 1 25 tem p er a t u re [ ] h y steresis [ % ] r 5 1 0x n 2 7 1 a/ c r 5 1 0xg2 7 1 a/ c 3 . 0 4 . 0 5 . 0 6 . 0 7. 0 - 50 - 25 0 25 50 7 5 1 00 1 25 tem p er a t u re [ ] h y steresis [ % ]
R5107G ( preliminar y) 12 r 5 1 0x n 42 1 a/ c r 5 1 0xg42 1 a/ c 3 . 000 4 . 000 5 . 000 6 . 000 7. 000 - 50 - 25 0 25 50 7 5 1 00 1 25 tem p er a t u re [ ] h y steresis [ % ]
R5107G ( preliminar y) 13 4) nch driver output current vs. v ds topt=25 c 5) nch driver output current vs. v dd 6) pch driver output current vs. v dd r 5 1 0x n , r 5 1 0xg 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 20 0 . 00 . 20 . 40 . 60 . 8 1 . 0 1 . 2 1 . 4 vds [ v ] ou t pu t c u rrent [ m a] vdd=1.0v vdd=6.0v vdd=5.0v vdd=4.0v vdd=3.0v vdd=2.0v vdd=1.5v r 5 1 0x n , r 5 1 0xg 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 20 0 1 23456 s upp l y v o lt ag e v dd [ v ] ou t pu t c u rrent [ m a] vd s = 0 . 3 v 1 05 25 topt=- 40 r 5 1 0x n , r 5 1 0xg 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 20 0 1 23456 s upp l y v o lt ag e v dd [ v ] ou t pu t c u rrent [ m a] vds=0.5v 105 25 topt=-40 r 5 1 0x n , r 5 1 0xg 0 . 0 0 . 2 0 . 4 0 . 6 0 . 8 1 . 0 1 . 2 1 . 4 1 . 6 1 . 8 2 . 0 0 1 23456 s upp l y v o lt ag e [ v ] ou t pu t c u rrent [ m a] vds= 0 . 3 v 1 05 25 -40 r 5 1 0x n , r 5 1 0xg 0 . 0 0 . 2 0 . 4 0 . 6 0 . 8 1 . 0 1 . 2 1 . 4 1 . 6 1 . 8 2 . 0 0 1 23456 s upp l y v o lt ag e [ v ] ou t pu t c u rrent [ m a] vds= 0 . 5 v 1 05 25 -40
R5107G ( preliminar y) 14 7) released delay time vs. input voltage 8) released delay time vs. temperature 9) detector output delay time vs. temperature 10) wdt reset timer vs. temperature r 5 1 0x n , r 5 1 0xg 0 . 0 0 . 2 0 . 4 0 . 6 0 . 8 1 . 0 1 . 2 1 . 4 1 . 6 1 . 8 2 . 0 0 1 23456 s upp l y v o lt ag e [ v ] ou t pu t c u rrent [ m a] vds= 1 . 0 v 1 05 25 -40 r 5 1 0x n , r 5 1 0xg 300 320 340 360 380 400 420 440 460 480 500 - 50 - 25 0 25 50 7 5 1 00 1 25 1 50 tem p er a t u re [ ] po wer o n reset del ay tplh [ m s] vdd= 6 v r 5 1 0x n , r 5 1 0xg 300 320 340 360 380 400 420 440 460 480 500 - 50 - 25 0 25 50 7 5 1 00 1 25 1 50 tem p er a t u re [ ] po wer o n reset del ay tplh [ m s] vdd= 6 v r 5 1 0x n , r 5 1 0xg 0 1 0 20 30 40 50 60 7 0 80 9 0 1 00 - 50 - 25 0 25 50 7 5 1 00 1 25 tem p er a t u re [ ] time [us ec ] (-vdet)+ 1 (-vdet)- 1 1 us in pu t r 5 1 0x n , r 5 1 0xg 32 34 36 38 40 42 44 46 48 50 52 - 50 - 25 0 25 50 7 5 1 00 1 25 tem p er a t u re [ ] reset time [ m s ec ]
R5107G ( preliminar y) 15 11) wdt timeout period vs. temperature 12) wdt reset timer vs. input voltage 13) wdt timeout period vs. input voltage r 5 1 0x n , r 5 1 0xg 280 300 320 340 360 380 400 420 440 460 480 - 50 - 25 0 25 50 7 5 1 00 1 25 tem p er a t u re [ ] timeo u t p eriod [ m s ec ] r 5 1 0x n , r 5 1 0xg 32 34 36 38 40 42 44 46 48 50 52 1 23456 s upp l y v o lt ag e [ v ] reset time [ m s ec ] r 5 1 0x n , r 5 1 0xg 280 300 320 340 360 380 400 420 440 460 480 1 23456 s upp l y v o lt ag e [ v ] timeo u t p eriod [ m s ec ]

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